1. Field of the Invention
The present invention relates to a semiconductor structure and a fabrication method for the semiconductor structure, pertaining primarily to an SGT CMOS technique.
2. Description of the Background Art
A CMOS (complementary metal-oxide semiconductor) technique, one of the elemental techniques for a very-large-scale integrated circuit (VLSI), is capable of forming literally tens of millions of transistors as a single integrated circuit. In the CMOS technique, there is a strong need for allowing ever-increasing device element density to be further increased.
With a view to increasing the number of high-performance transistors, one type of field-effect transistor (FET), called “surrounding gate transistor (SGT)”, has been proposed. As advantages of using the SGT, it is expected to suppress short channel effects (SCE) so as to reduce a leak current and obtain an ideal switching operation. In addition, a gate region can be enlarged, which allows the SGT to have an enhanced current control function without increasing a gate length.
As a way to facilitate a reduction in size of each CMOS device element while maintaining satisfactory performance, it is contemplated to increase carrier mobility of a semiconductor material. In a CMOS device, an electron is used as a carrier for an N-channel FET, and a hole is used as a carrier for a P-channel FET. The carrier in a semiconductor substrate is forced by an electric field applied to the substrate, wherein an electron and a hole are accelerated in respective opposite directions along the electric field. A velocity of the carrier, called “drift velocity, is proportional to an intensity of the applied electric field. A proportionality constant between the drift velocity and the electric field intensity is the carrier mobility. Along with an increase in carrier mobility, a current density becomes higher, and consequently a transistor switching speed becomes higher.
In a conventional planar CMOS device, carrier mobility in each device element varies depending on various factors, particularly, largely on a surface of a wafer. Specifically, a carrier is influenced by atomic periodicity (a pattern formed by atoms) dependent on a crystal plane. Thus, any planar device element has carrier mobility dependent on a crystal plane on which it is formed. Further, even if a channel direction of a planar FET formed on a certain crystal plane is changed, a carrier mobility stays constant.
In the conventional CMOS technique, a silicon substrate having a (100) crystal plane (i.e., a surface orientation of (100)) is used. The reason for selection of the silicon substrate having the (100) crystal plane is that (a) when a surface of a silicon substrate is formed along a (100) crystal plane, a surface state density between the silicon substrate and a silicon oxide film is minimized, and (b) electron mobility in the (100) crystal plane is greater than those in other crystal planes, and therefore a source-drain current in an N-channel FET formed on the semiconductor substrate having the (100) crystal plane is maximized. Differently, hole mobility is not maximized in the (100) crystal plane, and consequently a source-drain current in a P-channel FET formed on the semiconductor substrate having the (100) crystal plane becomes smaller. Thus, even if the N-channel FET exhibits excellent characteristics, the P-channel FET cannot have desired characteristics. If the P-channel FET is formed on a (110) crystal plane, the hole mobility is increased particularly when a high electric field is applied thereto. However, the (110) crystal plane has not been used in the conventional planar CMOS device, because the electron mobility deteriorates in the (110) crystal plane. It may also be said that the (100) crystal plane has been used in the conventional planar CMOS device, as a result of compromise between respective maximizations of the hole mobility and the electron mobility, in a situation where it is unable to use a different crystal plane for each device element.
As shown in FIGS. 85(a) to 85(c), an SGT CMOS device has been proposed in various prior art documents (see the following Non-Patent Documents 1 to 3 and Patent Document 1). FIG. 85(a) shows that an SGT CMOS device makes it possible to reduce a device area as compared with a planar CMOS device. FIG. 85(b) shows a circuit, a layout and structure of the SGT CMOS device.
A FinFET CMOS device using various crystal planes has also been proposed (see the following Patent Documents 2 and 3). As shown in FIG. 85(c), a FinFET CMOS inverter 300 is formed by a paired set of a PFET 302 and an NFET 308. Respective drains 306, 312 of the PFET 302 and the NFET 308 are connected to each other through a line 316 to have an output potential (Out), and respective gates 305, 311 of the PFET 302 and the NFET 308 are connected to each other through a gate conductor 314 to have an input potential (In). The FinFET CMOS inverter 300 comprising the above paired set is supplied with a power supply voltage (Vdd) through a line 317 connected to a source of the PFET 302, and connected to ground (Gnd) through a line 318 connected to a source 310 of the NFET 308. However, in each of the Patent Documents 2 and 3, crystal orientation and carrier mobility related to the crystal orientation have not been taken into account.
Thus, there remains a possibility that the SGT CMOS technique is improved by using various crystal planes in association with a current channel type and a pillar shape of an FET. In this case, it is considered that a desired performance of each CMOS device element can be maintained by optimizing carrier mobility or reducing carrier mobility in each device element, depending on a specific intended purpose.
As another approach to improving performance of each CMOS SGT, it is contemplated to select an optimal one of various shapes (cross-sectionally circular shape, square shape, etc) of a silicon pillar. A value of carrier mobility varies depending on a surface orientation of a sidewall of the silicon pillar. In other words, a shape and a surface orientation of the silicon pillar have an impact on carrier mobility. Further, physical properties (electric field, local carrier mobility, etc) of the device element are changed by changing the shape of the SGT pillar. An electric field is locally dependent on a structure of the SGT pillar, for example, where a curvature radius of a corner or an overall size in cross-section thereof is reduced, so that a change in perpendicular electric field causes a significant change in performance of the device element.                Patent Document 1: U.S. Pat. No. 5,258,635        Patent Document 2: U.S. Pat. No. 6,815,277        Patent Document 3: U.S. Pat. No. 6,658,259        Non-Patent Document 1: IEEE Trans. Electron Dev., Vol. 38(3), pp. 579-583 (1991)        Non-Patent Document 2: IEDM Tech. Dig., p. 736 (1987)        Non-Patent Document 3: The Japanese Journal of Applied Physics (JJAP), Vol. 43(10), p. 6904 (2004)        